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The original work was prepared by Dr. Lynn P. Gate-Level Modeling Modeling using basic Verilog gate primitives, description of andlor and buflnot type gates, rise, fall and turn-off delays, min, max, and typical delays. Dataflow Modeling Continuous assignments, delay specification,expressions, operators, operands, operator types.
Behavioral Modeling Structured procedures, initial and always, blocking'and nonblocking statements, delay control, event control, conditional statements,multiway branching, loops, sequential and parallel blocks. Tasks and Functions Differencesbetween tasks and functions, declaration, invocation.
Useful Modeling Techniques Procedural continuous assignments, overriding parameters, conditional compilation and execution, useful system tasks. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip.
As technologies became sophisticated, designers were able to place circuits with hundreds of gates on a chip. At this point, design processes started getting very complicated, and designers felt the need to automate these processes. Chip designers began to use circuit and logic simulation techniques to verify the functionality of building blocks of the order of about transistors. The circuits were still tested on the breadboard, and the layout was done on paper or by hand on a graphic computer terminal.
Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer-aided techniques became critical for verification and design of VLSI digital circuits. Computer programs to do automatic placement and routing of circuit layouts also became popular. The designers were now building gate-level digital circuits manually on graphic terminals. They would build small building blocks and then derive higher-level blocks from them.
This process would 1. Technically, the term Computer-Aided Design C A D tools refers to back-end tools that perform functions related to place and route, and layout of the chip. For the sake of simplicity, in this book, we will refer to all design tools as C A D tools.
Logic simulators came into existence to verify the functionality of these circuits before they were fabricated on chip. As designs got larger and more complex, logic simulation assumed an important role in the design process. Designers could iron out functional bugs in the architecture before the chip was designed further. Similarly, in the digital design field, designers felt the need for a standard language to describe digital circuits.
HDLs allowed the designers to model the concurrency of processes found in hardware elements. Both verilogB and VHDL simulators to simulate large digital circuits quickly gained acceptance from designers.
Even though HDLs were popular for logic verification, designers had to manually translate the HDL-based design into a schematic circuit with interconnections between gates. The advent of logic synthesis in the late s changed the design methodology radically.
Thus, the designer had to specify how the data flows between registers and how the design processes the data. The details of gates and their interconnections to implement the circuit were automatically extracted by logic synthesis tools from the RTL description. Thus, logic synthesis pushed the HDLs into the forefront of digital design.
Designers no longer had to manually place gates to build digital circuits. They could describe complex circuits at an abstract level in terms of functionality and data flow by designing those circuits in HDLs.
Logic synthesis tools would implement the specified functionality in terms of gates and gate interconnections. HDLs also began to be used for system-level design. A common approach is to design each IC chip, using an HDL, and then verify system functionality via simulation. Unshaded blocks show the level of design representation; shaded blocks show processes in the design flow. In any design, specifications are written first.
Specifications describe abstractly the functionality, interface, and overall architecture of the digital circuit to be designed. At this point, the architects do not need to think about how they will implement this circuit. A behavioral description is then created to analyze the design in terms of functionality, performance, compliance to standards, and other high-level issues. Behavioral descriptions can be written with HDLs. The designer has to describe the data flow that will implement the desired digital circuit.
Logic synthesis tools convert the RTL description to a gate-level netlist. A gate- level netlist is a description of the circuit in terms of gates and connections between them. The gate-level netlist is input to an Automatic Place and Route tool, which creates a layout. The layout is verified and then fabricated on chip. Thus, most digital design activity is concentrated on manually optimizing the RTL description of the circuit.
Designing at RTL level has shrunk design cycle times from years to a few months. It is also possible to do many design iterations in a short period of time.
Behavioral synthesis tools have begun to emerge recently. These tools can create RTL descriptions from a behavioral or algorithmic description of the circuit. As these tools mature, digital circuit design will become similar to high-level computer programming. Designers will simply implement the algorithm in an HDL at a very abstract level. CAD tools will help the designer convert the behavioral description to a final IC chip.
It is important to note that although CAD tools are available to automate the processes and cut design cycle times, the designer is still the person who controls how the tool will perform. If used improperly, CAD tools will lead to inefficient designs. Thus, the designer still needs to understand the nuances of design methodologies, using CAD tools to obtain an optimized design.
Designs can be described at a very abstract level by use of HDLs. Designers can write their RTL description without choosing a specific fabrication technology. If a new technology emerges, designers do not need to redesign their circuit. They simply input the RTL description to the logic synthesis tool and create a new gate-level netlist, using the new fabrication technology. The logic synthesis tool will optimize the circuit in area and timing for the new technology.
By describing designs in HDLs, functional verification of the design can be done early in the design cycle. Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality. Most design bugs are eliminated at this point.
This cuts down design cycle time significantly because the probability of hitting a functional bug at a later time in the gate-level netlist or physical layout is minimized. Designing with HDLs is analogous to computer programming. A textual description with comments is an easier way to develop and debug circuits. This also provides a concise representation of the design, compared to gate- level schematics. Gate-level schematics are almost incomprehensible for very complex designs.
HDLs are most certainly a trend of the future. With rapidly increasing complexities of digital circuits and increasingly sophisticated CAD tools, HDLs will probably be the only method for large digital designs. No digital circuit designer can afford to ignore HDL-based design. Verilog HDL offers many useful features for hardware design.
Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is similar in syntax to the C programming language. Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a hardware model in terms of switches, gates, RTL, or behavioral code.
Also, a designer needs to learn only one language for stimulus and hierarchical design. Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for designers.
Thus, designing a chip in Verilog HDL allows the widest choice of vendors. The Programming Language Interface PLI is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. Designers have responded by designing at higher levels of abstraction. Designers have to think only in terms of functionality. CAD tools take care of the implementation details.
With designer assistance, CAD tools have become sophisticated enough to do a close-to-optimum implementation. Behavioral synthesis has recently emerged. As these tools improve, designers will be able to design directly in terms of algorithms and the behavior of the circuit, and then use CAD tools to do the translation and optimization in each phase of the design. Behavioral modeling will be used more and more as behavioral synthesis matures.
Until then, RTL design will remain very popular. Formal verification techniques are also appearing on the horizon. Formal verification applies formal mathematical techniques to verify the correctness of Verilog HDL descriptions and to establish equivalency between RTL and gate- level netlists.
However, the need to describe a design in Verilog HDL will not go away. For very high speed and timing-critical circuits like microprocessors, the gate- level netlist provided by logic synthesis tools is not optimal. In such cases, designers often mix gate-level description directly into the RTL description to achieve optimum results. This practice is opposite to the high-level design paradigm, yet it is frequently used for high-speed designs because designers need to squeeze the last bit of timing out of circuits and CAD tools sometimes prove to be insufficient to achieve the desired results.
A trend that is emerging for system-level design is a mixed bottom-up methodology where the designers use either existing Verilog HDL modules, basic building blocks, or vendor-supplied core blocks to quickly bring up their system simulation. This is done to reduce development costs and compress design schedules. The designer must use a "good" design methodology to do efficient Verilog HDL- based design.
In this chapter, we discuss typical design methodologies and illustrate how these concepts are translated to Verilog. A digital simulation is made up of various components. We talk about the components and their interconnections. Learning Objectives Understand top-down and bottom-up design methodologies for digital design. Describe four levels of abstraction-behavioral, data flow, gate level, and switch level-to represent the same module.
Describe components required for the simulation of a digital design. Define a stimulus block and a design block. Explain two methods of applying stimulus. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. Figure shows the top-down design process.
Top level - 5 5 Figure Top-down Design Methodology In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higher-level blocks until we build the top-level block in the design. Figure shows the bottom-up design process. Design architects define the specifications of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks.
At the same time, circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. To illustrate these hierarchical modeling concepts, let us consider the design of a negative edge-triggered Cbit ripple carry counter described in Section 2. The diagram for the design hierarchy is shown in Figure I Rivvle Carrv I hL1 Inverter Figure Design Hierarchy In a top-down design methodology, we first have to specify the functionality of the ripple carry counter, which is the top-level block.
Then, we implement the counter with T-FFs. Thus, we break bigger blocks into smaller building sub-blocks until we decide that we cannot break up the blocks any further.
A bottom-up methodology flows in the opposite direction. Thus, the bottom-up flow meets the top- down flow at the level of the D-FF. Verilog provides the concept of a module. A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface inputs and outputs , but hides the internal implementation.
This allows the designer to modify module internals without affecting the rest of the design. In Verilog, a module is declared by the keyword module. A corresponding keyword endmodule must appear at the end of the module definition.
Each module must have a module-name, which is the identifier for the module, and a module-terminal-list, which describes the input and output terminals of the module. Internals of each module can be defined at four levels of abstraction, depending on the needs of the design. The module behaves identically with the external environment irrespective of the level of abstraction at which the module is described.
The internals of the module are hidden from the environment. Thus, the level of abstraction to describe a module can be changed without any change in the environment. These levels will be studied in detail in separate chapters later in the book.
The levels are defined below. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming. Dataflow level At this level the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design.
Gate level The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gate-level logic diagram.
Switch level This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switch-level implementation details. Verilog allows the designer to mix and match all four levels of abstractions in a design. In the digital design community, the term register transfer level RTL is frequently used for a Verilog description that uses a combination of behavioral and dataflow constructs and is acceptable to logic synthesis tools.
If a design contains four modules, Verilog allows each of the modules to be written at a different level of abstraction. As the design matures, most modules are replaced with gate-level implementations.
Normally, the higher the level of abstraction, the more flexible and technology independent the design. As one goes lower toward switch-level design, the design becomes technology dependent and inflexible. A small modification can cause a significant number of changes in the design. Consider the analogy with C programming and assembly language programming.
The program can be easily ported to any machine. However, if you design at the assembly level, the program is specific for that machine and cannot be easily ported to another machine.
When a module is invoked, Verilog creates a unique object from the template. The process of creating objects from a module template is called instantiation, and the objects are called instances. Each instance must be given a unique name. It instantiates 4 T-flipflops. Each instance is passed a set of signals. It instantiates a D-flipflop. Call it dff0. Explained later. I endmodule In Verilog, it is illegal to nest modules.
One module definition cannot contain another module definition within the module and endmodule statements. Instead, a module definition can incorporate copies of other modules by instantiating them. It is important not to confuse module definitions and instances of a module. Module definitions simply specify how the module will work, its internals, and its interface.
Modules must be instantiated for use in the design. Example shows an illegal module nesting where the module T-FF is defined inside the module definition of the ripple carry counter. The functionality of the design block can be tested by applying stimulus and checking results. We call such a block the stimulus block. It is good practice to keep the stimulus and design blocks separate. The stimulus block can be written in Verilog.
The stimulus block is also commonly called a test bench. Different test benches can be used to thoroughly test the design block. Two styles of stimulus application are possible. In the first style, the stimulus block instantiates the design block and directly drives the signals in the design block. In Figure , the stimulus block becomes the top-level block. It manipulates signals clk and reset, and it checks and displays output signal 9. Stimulus block clk reset Ripple Carry Counter Figure Stimulus Block Instantiates Design Block The second style of applying stimulus is to instantiate both the stimulus and design blocks in a top-level dummy module.
The stimulus block interacts with the design block only through the interface. This style of applying stimulus is shown in Figure The stimulus module drives the signals d-clk and d-reset, which are connected to the signals clk and reset in the design block. It also checks and displays signal c-q, which is connected to the signal q in the design block. The function of top-level block is simply to instantiate the design and stimulus blocks. We will define the design block and the stimulus block.
We will apply stimulus to the design block and monitor the outputs. As we develop the Verilog models, you do not need to understand the exact syntax of each construct at this stage. At this point, you should simply try to understand the design process.
We discuss the syntax in much greater detail in the later chapters. First, we write the Verilog description of the top-level design block Example , which is the ripple carry counter see Section 2. Therefore, we must now define Example the internals of the module T-FF, which was shown in Figure We assume asynchronous reset for the D-FF. Ignore the functionality of the constructs. The design block is now complete. In this case, we must control the signals clk and reset so that the regular function of the ripple carry counter and the asynchronous reset mechanism are both tested.
We use the waveforms shown in Figure to test the design. Waveforms for clk, reset, and 4-bit output q are shown. The cycle time for clk is 10 units; the reset signal stays up from time 0 to 15 and then goes up again from time to Output q counts from 0 to We will use the stimulus style shown in Figure Do not worry about the Verilog syntax at this point.
Simply concentrate on how the design block is instantiated in the stimulus block. The output obtained when stimulus and design blocks are simulated is shown in Example Two kinds of design methodologies are used for digital design: top-down and bottom-up. A combination of these two methodologies is used in today's digital designs.
As designs become very complex, it is important to follow these structured approaches to manage the design process. Modules are used in a design by instantiation. An instance of a module has a unique identity and is different from other instances of the same module. Each instance has an independent copy of the internals of the module. It is important to understand the difference between modules and instances.
There are two distinct components in a simulation: a design block and a stimulus block. A stimulus block is used to test the design block. The stimulus block is usually the top-level block. There are two different styles of applying stimulus to a design block.
The example of the ripple carry counter explains the step-by-step process of building all the blocks required in a simulation. This chapter is intended to give an understanding of the design process and how Verilog fits into the design process. The details of Verilog syntax are not important at this stage and will be dealt with in later chapters. You do not need to define the internals. Assume that the modules have no terminal lists.
Assume that the module IS has no terminals. Instantiate the design block IS and call the instance isl. This is the final step in building the simulation environment. Define the module FA. Do not define the internals or the terminal list. Define the module Ripple-Add. Instantiate four full adders of the type FA in the module Ripple-Add and call them faO, fal, fa2, and fa3. These conventions and constructs are used throughout the later chapters. These conventions provide the necessary framework for Verilog HDL.
Data types in Verilog model actual data storage and switch elements in hardware very closely. This chapter may seem dry, but understanding these concepts is a necessary foundation for the successive chapters.
Learning Objectives Understand lexical conventions for operators, comments, whitespace, numbers, strings, and identifiers. Define the logic value set and data types such as nets, registers, vectors, numbers, simulation time, arrays, parameters, memories, and strings. Identify useful system tasks for displaying and monitoring information, and for stopping and finishing the simulation.
Learn basic compiler directives to define macros and include files. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords.
Verilog HDL is a case-sensitive language. All keywords are in lowercase. Whitespace is ignored by Verilog except when it separates tokens. Whitespace is not ignored in strings. There are two ways to write comments. Verilog skips from that point to the end of line. Multiple-line comments cannot be nested. Unary operators precede the operand. Binary operators appear between two operands.
Ternary operators have two separate operators that separate three operands. Legal base formats are decimal 'd or 'D , hexadecimal 'h or 'H , binary 'b or 'B and octal '0 or '0. The number is specified as consecutive digits from O , 1 , 2 , 3 , 4,5, 6, 7, 8, 9, a, b, c, d, e, f. Only a subset of these digits is legal for a particular base. Uppercase letters are legal for number specification.
These values are very important for modeling real circuits. An unknown value is denoted by an X. A high impedance value is denoted by z.
If the most significant bit of a number is of X, or z, the number is automatically extended to fill the most significant bits, respectively, with 0, X, or z. This makes it easy to assign X or z to whole vector. If the most significant digit is I, then it is also zero extended. Size constants are always positive.
Underscore characters are allowed only to improve readability of numbers and are ignored by Verilog. A question mark "? Note that? The restriction on a string is that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple lines. Keywords are in lowercase.
Identifiers start with an alphabetic character or an underscore. All characters between backslash and whitespace are processed literally. The backslash or whitespace is not considered a part of the identifier. The four value levels are listed in Table Value levels o and 1can have the strength levels listed in Table For example, if two signals of strength strongl and weak0 contend, the result is resolved as a strongl.
If two signals of equal strengths are driven on a wire, the result is unknown. If two signals of strength strongl and strong0 conflict, the result is an X. Strength levels are particularly useful for accurate modeling of signal contention, MOS devices, dynamic MOS, and other low-level devices. Only t r i r e g nets can have storage strengths large, medium, and small. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to.
In Figure net a is connected to the output of and gate g l. Nets are one-bit values by default unless they are declared explicitly as vectors. The terms w i r e and net are often used interchangeably. The default value of a net is z except the t r i r e g net, which defaults to X. Nets get the output value of their drivers. If a net has no driver, it gets the value z.
Note that net is not a keyword but represents a class of data types such as w i r e , wand, wor, tri, triand, t r i o r , t r i r e g , etc. The w i r e declaration is used most frequently. Registers retain value until another value is placed onto them. Do not confuse the term registers in Verilog with hardware registers built from edge-triggered flip-flops in real circuits. In Verilog, the term register merely means a variable that can hold a value. Unlike a net, a register does not need a driver.
Verilog registers do not need a clock as hardware registers do. Values of registers can be changed anytime in a simulation by assigning a new value to the register. Register data types are commonly declared by the keyword reg. The default value for a reg data type is X. An example of how registers are used is shown Example If bit width is not specified, the default is scalar l-bit.
In the example shown above, bit 0 is the most significant bit of vector virtual-addr. For the vector declarations shown above, it is possible to address bits or parts of vectors. Integer An integer is a general purpose register data type used for manipulating quantities. Integers are declared by the keyword integer.
Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. The default width for an integer is the host-machine word size, which is implementation specific but is at least 32 bits. Registers declared as data type reg store values as unsigned quantities, whereas integers store values as signed quantities.
They can be specified in decimal notation e. Real numbers cannot have a range declaration, and their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer. A special time register data type is used in Verilog to store simulation time. A time variable is declared with the keyword time. The width for time register data types is implementation specific but is at least 64 bits. The unit is denoted by S , the same as real time.
However, the relationship between real time in the digital circuit and simulation time is left to the user. This is discussed in detail in Section 9. Arrays are not allowed for real variables. Multidimensional arrays are not permitted in Verilog. This is a 5-bit value. It is important not to confuse arrays with net or register vectors. A vector is a single element that is n-bits wide.
On the other hand, arrays are multiple elements that are l-bit or n-bits wide. Memories are modeled in Verilog simply as an array of registers. Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n l-bit registers and one n-bit register. A particular word in memory is obtained by using the address as a memory array subscript.
Parameters cannot be used as variables. Parameter values for each module instance can be overridden individually at compile time. This allows the module instances to be customized. This aspect is discussed later. Hardcoded numbers should be avoided. Parameters can be changed at module instantiation or by using the defparam statement, which is discussed in detail in Chapter 9, Useful Modeling Techniques. Thus, use of parameters makes the module definition flexible.
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